FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

IRQ in DSP Builder

Stratix iv - PLL & loop filter characterisation information

Placing the ALT2GXB on the EP2SGX90FF1508C3............

Where to connect the user app ? pici-e

Strange and random (!?) error of the Control block

DDR2 HPC2 Timing Simulation fails

Error in Altera 10Gbps MAC documentation

DDR2 controller local_ready goes low

Overlay moving (live) graphics feed on video

Clearing asyncram contents

VIP switch register readback

NCO MegaCore Function

PCI express - Clk Ref, application clk and recailbration clk

dynamic pll reconfiguration

setup for TSE without MAC (just PCS+PMA)

Featured Content

Tone Mapping Operator IP Malfunctioning

dynamic configuration issue of fpll from arria 10

AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0]

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)